The present invention relates to a vertical arrangement of at least two semiconductor components that are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement.
One example of such multichip semiconductor component arrangements is the chip-on-chip mounting of control ICs on the cell array of power transistors. Such an arrangement requires a correspondingly robust protective layer on the base chip (power transistor) in order to protect the latter from mechanical damage during mounting and later thermomechanical loading during operation of the components. At the same time, however, said protective layer is required to have no disadvantageous effects, or at any rate the least disadvantageous effects possible, on the reliability of the base chip, such as the drift of component parameters over the lifetime of the semiconductor component. Suitable materials for said passivation layer are materials with good properties as an electrical insulator, mechanical resistance and as a diffusion barrier, such as, silicon nitride, silicon oxide, boron nitride and diamond.
U.S. Pat. No. 4,947,234 describes an arrangement comprising a power semiconductor chip and a control circuit integrated in a second semiconductor chip. In this case, the semiconductor chip of the control circuit is applied to one of the top sides of the power semiconductor chip, the two semiconductor chips being connected to one another by an insulating layer, also passivation layer, and a soldering layer. The semiconductor chip with the control circuit is connected to the power semiconductor chip via electrical lines. The passivation layer, for example, a silicon nitride layer, usually has a uniform thickness of between 800 and 1600 nm over the entire semiconductor arrangement. By virtue of the different—by approximately a factor of 10—thermal expansion coefficients of the electrical lines made of an aluminum alloy or the molding composition of the housing and the relatively thick passivation layer, high thermomechanical loading arises, for example, when soldering in the semiconductor component, and may lead to cracks at the edges of the metallization. The cracks produced in this way may be transmitted to the power semiconductor component by the intermediate oxide and lead here to leakage currents or short circuits in the device. This effect is all the more pronounced, the thicker the passivation layers.
In order to protect the base chip, for example, the power transistor, adequately from mechanical loading of the top chip, for example, a control IC, the thickness of the passivation layer is typically limited to a minimum of 800 nm. Such mechanical loading by the top chip, so-called imprints, may originate inter alia from movements of the top chip, caused by, for example, thermal or mechanical loading of the housing. Depending on the method for fabricating the passivation layer, a further disadvantage may result from the use of thick passivation layers in that a high content of radical hydrogen intensifies the threshold voltage drift of the MOS transistor after high-temperature gate stress.